If 'dff' happened to want to also drive the bit to '0', then the result would be '0'. For example, if the process is trying to set Q_sig(1) to a value of '1', but 'dff' is trying to set it to '0', then the result is an 'X'. So you have two things driving 'Q_sig' which will cause unknowns as well if the process and the flip flop don't happen to agree on what they are driving.
But the four instances of 'dff' also drives these bits. Q_sig <= D_sig end if end process end bhv Q_sig : out std_logic_vector ( 1 to 4 ) ) end bitreg4 architecture bhv of bitreg4 is beginĭff1 : entity work.dff port map (d => D_sig ( 1 ), preset => ' 0', clear => ' 1', clk => Clk_sig,q => Q_sig ( 1 ) ) ĭff2 : entity work.dff port map (d => D_sig ( 2 ), preset => ' 0', clear => ' 1', clk => Clk_sig,q => Q_sig ( 2 ) ) ĭff3 : entity work.dff port map (d => D_sig ( 3 ), preset => ' 0', clear => ' 1', clk => Clk_sig,q => Q_sig ( 3 ) ) ĭff4 : entity work.dff port map (d => D_sig ( 4 ), preset => ' 0', clear => ' 1', clk => Clk_sig,q => Q_sig ( 4 ) ) process (Clk_sig,D_sig,Load ) begin if Load = ' 1' then Load : in std_logic -D : in std_logic_vector(1 to 4) all use work.dff entity bitreg4 is port (Clk_sig : in std_logic
